1. Field of the Invention
The present invention relates generally to LSI (large scale integration) chip testing, and more specifically to testing of LSI chips using expert systems.
2. Description of the Related Art
Conventional LSI memory testing involves the use of a memory tester with which a test engineer is engaged in a dialog mode to apply a test pattern to an LSI memory under test. The result of the test is obtained in a bitmap format, which is checked by the engineer to determine the next test pattern or determine the possible location of a fault. However, with the ever increasing memory capacity the amount of data to be manually analyzed is becoming difficult. To overcome this difficulty, T. Viacroze et al describe a memory testing system in a paper "Analysis of Failures on Memories Using Expert System Techniques", 1990 International Test Conference, in which an expert system is run on an IBM computer PS/2 connected to a memory tester. The system engages an operator in a dialog mode and provides expert advices for creating and executing additional tests until a solution is reached.
There is still a need to implement testing of LSI chips using expert systems without human intervention in order to minimize the amount of time involved with each LSI chip.